VLSI Technical Interview questions

1. What is Mux? explain..

I started explaining from a block diagram very patiently.

2. What is adder?  I stated from truth table and derived Sum , carry equations arrived at gate level realization.

3. Adder using Mux.I was bit confused .. I just wrote using 4:1 mux because I didn’t want to scramble with such simple question I just did as if I understood question as using 4:1 (I knew he is expecting using 2:1.. it was trick)

Then he asked me you do it using 2:1,but by then I had got some time fr myself..happens in interviews sometimes we get to struggle with simple questions.Then I did it using 2:1 Mux.

4. AND gate using Mux , OR gate using Mux.

5. What is latch and flip flop. Difference.

then he gave me clock and data timing diagram ,told me to draw output  for FF and latch. I assumed some delay for FF  and completed. I explained while drawing and kept interview interactive as much as possible.(it’s a trick any interviewers likes to hear more from you. .speak and speak it also builds confidence within you)..

6. draw counter : I selected to draw very simple  2-bit up counter and started drawing FF, I got doubt I asked him if Synch/Asynch counter. He told ‘Anything.. OK.. draw.. Synch counter. I tried using DFF not getting..(??) then immediately changed to TFF counter.. Then he asked me to draw using DFF. I said ‘Yes Sir I can'(speak positive though you don’t know immediately and take time to answer..)

Then I was trying with some mind calculation to get Q1Q0 as 00,01,10,11…I kept saying him whatever I was thinking in my mind.Then he interrupted and said me ‘Rekha, do you know a systematic approach for this ,if so try that.. ‘.. he was about to say States…But I got it by then and started explaining myself and completed counter design as a sequential machine.

7. Mod-2 counter the same way.. I did everything again sequential design..

8. What is set-up and hold time?What happens if not satisfied(Ans: Metastability word should come here)

9. Given a Flip Flop circuit how to determine maximum operable frequency..

I told (1/(Setup time+Flop delay)).. he expected it to be max(hold time, Flop delay). He asked me again and again what if delay is 0 and then immediately told my  previous answer is based on the assumption (hold time)< (Flop delay).

and we have to take max(hold time, Flop delay) in case of no assumption.

10. It’s a tricky and a new question to me: You have a digital system designed which has got set up time and hold time violations , you are allowed to fix only one problem(setup or hold) which one you choose and why?

I thought for sometime and drew some clock edges and marked set up and hold times.Tried to explain whatever I know.Interviewer was happy for the attempt and the explanation.

Updated Ans: generally setup time and hold time violations are very very serious concerns in the design.so if there are any setup/hold violations they are identified during the timing analysis (99.99999 % coverage is done for timing)… during the timing analysis if there is any setup violation, it can be avoided by adding clock buffers in the clock path or removing data buffers in the data path or some changes can be made to the design itself… similarly if there is a hold violation, clock buffers are removed or data buffers are added or design can be modified……
if by any chance once the chip is fabricated with:
1) setuptime violation: the way to function it properly is to reduce the frequency (basically by reducing the frequency of the clock u r increasing the time period and trying to avoid the setup violation).
2) hold violation: u cannot make any tweaks to function it properly, basically the chip goes in to trash…
so out of the two violations, hold violation is more dangerous.

Now my Tech questions over. he asked me two puzzles:

1. Balance puzzle

I just wrote down the puzzle on paper in detail with a figure of balance also..( to make him think you analyze things systematically and ant tech person will like that approach ). Here my interview skill won than my analysis/approach..So be tactful while answering questions both easy and tough..!!!!!!!Try to be more descriptive and interact no matter whether you land up with answer or not..But you find answers most of times when you solve problems interactively..

2. 125 small cubes given, make a big cube using  those and  all 6 faces of new cube panted red ,then how many faces of small cubes are painted??(This is new to me)

Then again I wrote down the problem.. started actually analyzing it.. thought of 5^3 =125 also.. wrote in a corner.. and thought again if I can say him immediately answer. No I ws not confident of my answer so just took more time..still thinking then he said do you know integration and imagine in 3D the cubes and try.. ” I said “Yes Sir I used to love integration in maths.. but don’t remember it exactly or a systematic way. ..”

He said “that’s fine Rekha we will wind up here I like to meet you in second round , you give me your answer then.. don’t ask friends.. think o your own..Nice to meet you .. pls come after lunch”..

Done with first round of Technical..Second round.

23 responses to “VLSI Technical Interview questions

  1. Pingback: Dream come True Day: The day I got placed with Qualcomm…:):) | DreamzZzZz…Z..z…

    • Out of three inputs(A,B,C) to FA: take any one of them (say C)as select line and draw a K-map to simplify output in terms of of other two assuming Select line as ‘1’ , will be expression at C=1, and repeat same to get expression when C=0 , supply input for C=0.
      two Muxes : 1 for sum and other to realise Carry..
      try out.. U will get it..

  2. i have qualified for interview ,but in interview they have asked about the b.tech project ,i did not answered it properly , rest they have asked about vlsi basics ,verilog for these questions i have answered properly.
    finally i did not select for qualcomm
    is there any chance to try for qualcomm .(actually qualcomm visited my campus on august 2,i am pursuing m.tech(microelectronics and vlsi )

  3. hello ma’am, i am b.tech student (completing in 2013)
    i am very much interested in vlsi and done six month training in vlsi.
    please tell me in which company i shall give interview as a fresher ?

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